The number of signal contact areas and supply contact areas is constantly increasing for large scale integrated semiconductor devices, while the area requirement per switching function is constantly decreasing. This is realized by advanced miniaturization of the circuit structures on a semiconductor chip with each new technology generation, which is usually characterized by the smallest feature sizes that can be attained, such as e.g. 130 nanometer technology, 90 bnanometer technology, 65 nanometer technology, etc. This large scale integration is furthermore fostered by a vertical integration of an increasing number of wiring planes, such as metal layer M1, metal layer M2, up to metal layer M(x−1) and M(x). However, the power consumption per function cannot be reduced to the same extent as the area requirement per function, so that the power densities of semiconductor ICs tend to increase.
In order to reduce the internal electric field strength, for example to enable the insulation distances to be halved, the supply voltages are constantly being reduced from, e.g., a 12 V technology through a 5 V technology, a 3.3 V technology, a 2.5 V technology to 1.8 V technology, etc. However, the reduction of the supply voltage, in conjunction with a simultaneously increasing power consumption, leads to ever higher currents. It thus turns out that in the case of communication ICs having a power consumption of P=3-4 W, depending on the supply voltage U, it is necessary to cope with currents I of 1 A to 2 A. These currents are intended to be distributed on the semiconductor chip to the switching function through metal cross-sections having the lowest possible resistance, in order to avoid local voltage dips. Wide low-resistance metal tracks on the semiconductor chip cost valuable semiconductor chip surface area, however, and entail potential reliability problems.
At the same time, as the integration density increases, the metal cross-sections decrease between the outer contact areas on the top side of a semiconductor chip and the topmost metallization plane of the integrated circuit and so their current-carrying capacity also decreases correspondingly. In the case of modern technologies, a current of 10 mA per contact area can typically be fed in at the present time. In order to feed a total current of I=1 A into the circuit, accordingly, 100 supply contact areas are required on the top side of the semiconductor chip for the introduction of the current of 1 A and, in addition, just as many ground contact areas are required in order to enable the current to flow away again.
In the case of semiconductor products having 200 to 1,000 connections which are being constructed as BGA devices (ball grid array devices) in the meantime, a very high proportion of the connections is thus required only as supply connections, so that, depending on the power consumption, up to half or more of these exterior contact connections have to be included in the design for supplying current to the supply contact areas on the top side of the semiconductor chip. In the interior of the semiconductor device, the wire bonding technique is often used, which involves having to produce in some instances long bonding wires lying close together, in which case production problems and production risks such as wire drifting or short circuits may occur. Consequently, the limit in terms of being able to realize such large scale integrated circuits is gradually being reached.
Moreover, at increasingly higher signal frequencies there is the risk of long and closely adjacent bonding wires increasing the inductance and/or the crosstalk, which can likewise impede product realization. The high number of supply connections that are to be contact-connected externally from a semiconductor chip thus becomes a problem from the standpoint of feasibility, performance and also production costs, particularly in the case of wire bonding contact-connections. In the case of the wire bonding contact-connection, the above-described densest possible contact-connection of supply contact areas and signal contact areas which are arranged at the semiconductor chip periphery and have to be led onto an organic or ceramic substrate is associated with the disadvantages and risks described above.
In the case of the flip-chip mounting technique, the production of many supply contact connections can be simplified, but expensive multilayer substrates with different metallization planes and plated-through holes are then required, and, in the case of the customary semiconductor chip patternings, a rewiring layer is required directly on the chip in order to reach the individual integrated circuit structures from the periphery signal contact areas and supply contact areas. In this case, such a rewiring layer on the semiconductor chip is to be adapted to the respective chip design in a disadvantageous manner, while greater flexibility is possible in the case of the wire bonding technique.
For power semiconductor devices, the problem of the supply connections is solved by means of metallic plate-type collective electrodes on the top side of the semiconductor device, as is disclosed in the U.S. Pat. No. 6,040,626. The patent application DE 103 49 477 also proposes, for a power MOSFET device, a collective electrode for all the source connections on the top side of the semiconductor chip, said electrode being arranged in plate-type fashion and being connected to corresponding exterior flat conductors of a flat conductor leadframe.